The present disclosure relates generally to an integrated circuit (IC) device and, more particularly, to a method for forming a complementary metal oxide semiconductor (CMOS) structure.
As technology nodes shrink, in some IC designs, there has been a desire to incorporate strained engineering, including a SiGe, a SiC, a SiP and/or a Si epitaxial (epi) process, in the formation process of CMOS devices to overcome Moore's law.
There are challenges to implementing such epi features and processes in CMOS fabrication. As technology nodes continue to decrease in size, particularly to the 22 nanometer (nm) technology node and below, the defect issue is one of the key challenges for forming the epi film. The defects may result from a removal process for removing a protective layer after the formation of epi lightly doped source/drain (LDD) features and/or epi source/drain (S/D) features. The defects which result in the CMOS device may impact the yield of device.